The present disclosure relates to a method of manufacturing semiconductor structures, and particularly to a method of repairing gap-fill keyholes in a planarization dielectric layer, and structures formed thereby.
Planarization dielectric layers are employed in semiconductor manufacturing to provide a dielectric material structure having a planar top surface. Planarization dielectric layers can be employed for various purposes including, but not limited to, providing a dielectric template that embeds disposable material structures that are selectively removed and replaced with permanent structures. For example, in a replacement gate integration scheme, disposable gate structures can be formed on a semiconductor substrate, and a planarization dielectric layer can be formed thereupon. The planarization dielectric layer is subsequently planarized to provide a horizontal top surface that is coplanar with topmost surfaces of the disposable gate structures. The disposable gate structures are then removed selective to the planarization dielectric layer. Cavities in the disposable gate structures are filled with materials to form permanent structures, which are also referred to as replacement structures.
Dielectric materials that are deposited over protruding structures can have gap-fill keyholes. Gap-fill keyholes are generally formed between a pair of structures protruding above a substrate when the spacing between the pair is narrow and/or the sidewalls of the pair do not have a sufficient taper. A “gap-fill keyhole” refers to any cavity within a dielectric material layer that results from the inability of a deposition process that deposits the dielectric material layer to completely fill a space between two or more neighboring protruding structures that are present prior to deposition of the dielectric material layer.
Gap-fill keyholes function as a trap for materials deposited over the dielectric material layer, especially if the top of the gap-fill keyhole is exposed by recessing an initial top surface of the dielectric material layer. When a conductive material is deposited over the dielectric material layer, the conductive material can be deposited within the dielectric material layer to form a conductive channel that electrically shorts device components or blocks subsequent attempts to etch contact holes within the dielectric material layer.